1. Field of Invention
The present invention relates to a switching control circuit, a semiconductor device and a switching power source apparatus having an overcurrent protection function for protecting a switching device.
2. Description of Related Art
In a switching power source apparatus for supplying a stable DC voltage to a load, current limitation is generally provided to prevent a current having a predetermined value or more from flowing through a switching device. However, at the starting time and an overload time in which the output voltage of the switching power source apparatus is low, the current having the predetermined value or more flows through the switching device, that is, the so-called overcurrent state of the switching device occurs, and the current may become equal to or larger than the allowable current value of the switching device in some cases. For the purpose of preventing the switching device from being degraded and damaged by the overcurrent, in the case that the overcurrent state of the switching device occurs, protection is required to suppress the current flowing through the switching device from increasing or to reduce the current immediately.
First, in a conventional switching power source apparatus, the causes of the overcurrent state of the switching device will be described below.
FIG. 16 is a block diagram showing a configuration example of a conventional switching power source apparatus. This switching power source apparatus is a flyback power source equipped with a switching transformer 101 having a primary winding 101a and a secondary winding 101b. A switching device 103 in a switching control circuit 102 is connected in series with the primary winding 101a, and an input voltage VINp is applied to the primary winding 101a and the switching device 103. The switching device 103 is ON/OFF controlled by a control circuit 104, and power is transferred from the primary winding 101a to the secondary winding 101b of the switching transformer 101.
The AC voltage induced across the secondary winding 101b of the switching transformer 101 by the ON/OFF operation (hereafter referred to as a switching operation) of the switching device 103 is rectified and smoothed by an output voltage generating circuit 105 containing a diode 105a and a capacitor 105b, whereby an output voltage VOUTp is generated and supplied to a load 106. This output voltage VOUTp is detected by an output voltage detection circuit 107, and a feedback signal FB_Sp corresponding to the voltage level of the output voltage VOUTp is fed back to the control circuit 104. Hence, the switching operation is controlled and energy to be supplied to the load 106 is adjusted, whereby the output voltage VOUTp is stabilized to a predetermined voltage.
FIG. 17 is a block diagram showing a configuration example of the conventional switching control circuit 102 for use in the switching power source apparatus.
In FIG. 17, the switching control circuit 102 contains the switching device 103 and the control circuit 104. Current mode PWM control is adopted as a method for controlling the ON/OFF operation of the switching device 103.
When the switching device 103 is turned ON, a device current IDp flowing through the switching device 103 is detected by a device current detection circuit 111, and the device current IDp is compared with a target level IL_1p in a comparison circuit 112. When the level of the device current IDp becomes higher than the target level IL_1p, the comparison circuit 112 outputs a comparison result signal OC_1p corresponding to the result of the comparison as an input signal to an AND circuit 113. Another input signal of the AND circuit 103 is output from a blanking pulse generating circuit 114. This input signal is a blanking pulse signal BLKp for preventing the switching device 103 from being turned OFF for a constant period (hereafter referred to as a blanking period TBLKp) after the switching device 103 was turned ON. This blanking period TBLKp is provided to prevent a malfunction in which the switching device 103 is turned OFF by a spike current flowing through the switching device 103 immediately after the switching device 103 was turned ON.
Hence, control is performed so that the comparison result signal OC_1p is output from the comparison circuit 112 and an output signal OFF_1p is output from the AND circuit 113 after the blanking period TBLKp has passed to turn OFF the switching device 103. Furthermore, a delay time Td exists between the time when the device current IDp is detected to have become higher than the target level IL_1p at the comparison circuit 112 and the time when the switching device 103 is actually turned OFF.
In other words, in the switching control circuit 102, the device current IDp is limited by the comparison circuit 112 so that the level of the device current IDp does not become the target level IL_1p or more. In addition, the switching device 103 is configured so as to be turned ON for a period not less than a minimum ON period Tonminp determined by the sum of the blanking period TBLKp and the delay time Td.
Herein, in the switching power source apparatus, operation at the starting time in which the input voltage VINp is applied and the output voltage VOUTp has not yet risen will be described below. FIG. 18 is a timing chart showing the timing of the operation performed at this time.
As shown in FIG. 18, when the input voltage VINp rises, the PWM control of the switching device 103 is started, and the device current IDp flows periodically. However, since the output voltage VOUTp is low, as the input voltage VINp rises, the ON period of the switching device 103 becomes shorter each time a pulse is generated. If the ON period of the switching device 103 becomes short to the minimum ON period Tonminp in a clock period C2p, the switching device 103 is surely turned ON for only the minimum ON period Tonminp in each clock period, and the current limitation of the device current IDp by the comparison circuit 112 of the control circuit 104 does not work. For this reason, an overcurrent state occurs in which the device current IDp having a level equal to or more than the target level IL_1p flows through the switching device 103 for the minimum ON period Tonminp in the clock period C2p and thereafter. Furthermore, as the time passes in the order of a clock period C3p and a clock period C4p, the device current IDp increases. If the device current IDp reaches the allowable current value or more of the switching device 103, there is a fear of degrading and damaging the switching device 103.
Next, overcurrent protection for the switching device in the conventional switching power source apparatus will be described below.
For example, in the switching control circuit disclosed in U.S. Patent Application Publication No. 2007/0008753 A1 (corresponding to Japanese Laid-open Patent Publication No. 2007-20394), the state obtained at the time when the level of the device current flowing through the switching device became higher than the limit level for overcurrent detection is detected as the overcurrent state of the switching device, and the frequency of the switching operation is switched to a lower frequency, whereby overcurrent protection is achieved.
FIG. 19 is a block diagram showing a configuration example of this switching control circuit. Blocks corresponding to the blocks constituting the switching control circuit shown in FIG. 17 are designated by the same numerals, and their descriptions are omitted.
In a switching control circuit 102a shown in FIG. 19, the device current IDp is compared by a comparison circuit 120 with a limit level signal IL_2p that is preset so as to be higher than the target level IL_1p in the comparison circuit 112, and a comparison result signal OC_2p is output from this comparison circuit 120. After the blanking period TBLKp has passed, an output signal OFF_2p output from an AND circuit 121 is input to a frequency control circuit 123 via a flip-flop circuit 122. Then, the clock frequency of a clock generating circuit 116 is controlled using an output signal FRQ_Cp from this frequency control circuit 123.
FIG. 20 is a timing chart showing the timing of overcurrent protection operation in the case that this switching control circuit 102a is used for the switching power source apparatus shown in FIG. 16, for example.
The ON period of the device current ID2p being subjected to overcurrent protection and shown in FIG. 20 becomes short to the minimum ON period Tonminp in the clock period C2p as described above. Furthermore, the frequency control circuit 123 detects the state obtained at the time when the level of the device current ID2p rose to the limit level signal IL_2p as shown in a waveform portion F20a as the overcurrent state of the switching device, and switches the clock frequency of the clock generating circuit 116 to a lower frequency. As a result, the OFF period Toff1p of the device current ID2p in the switching operation becomes longer than the OFF period of the device current ID1p that is not subjected to overcurrent protection, and the device current ID2p lowers by a device current drop amount ID1p. As described above, overcurrent protection is achieved by suppressing the device current ID2p from increasing each time a pulse for the switching operation is generated.
Moreover, for example, a switching power source apparatus disclosed in U.S. Patent Application Publication No. 2007/0008756 A1 (corresponding to Japanese Laid-open Patent Publication No. 2007-20393) detects the state obtained at the time when the ON period of the switching device became shortened to a threshold period as the overcurrent state of the switching device, and the frequency of the switching operation is switched to a lower frequency as in the case of the switching control circuit shown in FIG. 19, whereby overcurrent protection is achieved.
FIG. 21 is a block diagram showing a configuration example of this switching control circuit. Blocks corresponding to the blocks constituting the switching control circuits shown in FIGS. 17 and 19 are designated by the same numerals, and their descriptions are omitted.
This switching control circuit 102b differs from the switching control circuit 102a shown in FIG. 19 in that the switching control circuit 102b is equipped with a short ON period detection circuit 124 instead of the comparison circuit 120 and the AND circuit 121. Three signals, an output signal ROFF_1p (the inverted signal of the output signal of the AND circuit 113), a blanking pulse signal BLKp and a control signal DRIVEp in the switching operation, are input to this short ON period detection circuit 124. Furthermore, the short ON period detection circuit 124 detects the state obtained at the time when the ON period of the switching device 103 became shortened to the threshold period by these three input signals as the overcurrent state of the switching device 103, and outputs an output signal ROFF_2p. 
The output signal ROFF_2p is input to the frequency control circuit 123 via the flip-flop circuit 122 as in the case of the switching control circuit 102a shown in FIG. 19. The frequency of the clock signal CLOCKp generated by the clock generating circuit 116 is controlled by an output signal FREQ_Cp from the frequency control circuit 123.
Hence, the switching control circuit 102b differs from the switching control circuit 102a shown in FIG. 19 in the configuration of detecting the overcurrent state of the switching device.
FIG. 22 is a timing chart showing timing at the starting time in the case that the switching control circuit 102b shown in FIG. 21 is used for the switching power source apparatus shown in FIG. 16, for example.
In FIG. 22, the state obtained at the time when the ON period of the switching device 103 became shortened to a threshold period Ton1p (FIG. 22 shows a case in which the threshold period Ton1p is equal to the minimum ON period Tonminp) is detected as the overcurrent state of the switching device 103, and the frequency of the clock signal CLOCKp generated by the clock generating circuit 116 is switched to a lower frequency. As a result, the OFF period Toff2p of the device current ID2p in the switching operation becomes longer, and the device current ID2p lowers by a device current drop amount ID2p. As described above, overcurrent protection is achieved by suppressing the device current ID2p from increasing each time a pulse for the switching operation is generated. The switching control circuit 102b activates overcurrent protection earlier than the case in which the switching control circuit 102a shown in FIG. 19 is used, that is, before the device current ID2p becomes large.